Semiconductor devices are developing to have high integration, high operation speed and low power consumption, which limit the application of bulk silicon substrates. On the contrary, Silicon on Insulator (SOT) substrates have advantages of dielectric isolation of devices in integrated circuit, complete elimination of parasitic latch-up effect in COMS circuit on bulk silicon substrate, low parasitic capacitance, high integration density, high speed, simple process, small short-channel effect, and applicability for low-power and low-voltage circuits. Therefore, SOT substrates are used more and more widely to form semiconductor devices. Radio Frequency (RF) devices require a small parasitic capacitance, in which substrate parasitic capacitance often plays a significant role. The parasitic capacitance can be effectively reduced by adopting a SOT substrate. In addition, high frequency characteristics and operating speed of RF devices may be improved when the RF devices are fabricated on SOT substrate.
A schematic structural diagram of a SOI RF device in the prior art is illustrated in FIG. 1. Referring to FIG. 1, a SOI substrate 1 includes a high resistivity silicon base 2, a Buried Oxide (BOX) layer 3 on the high resistivity silicon base 2, and a top silicon layer 4 on the BOX layer 3. A shallow trench isolation structure 5 is formed in the top silicon layer 4, so as to isolate active areas (not shown) in the top silicon layer 4. Semiconductor devices, such as transistors, are formed in the active areas of the top silicon layer 4. Metal interconnection structures are formed on the SOI substrate 1. As shown in FIG. 1, taking one layer Metal interconnection structure as an example, the one layer Metal interconnection structure includes: an interlayer dielectric layer 6 on the top silicon layer 4 and the shallow trench isolation structure 5, conductive plugs (not shown) formed in the interlayer dielectric layer 6, and a metal layer 7 on the interlayer dielectric layer 6 and the conductive plugs, where at least a part of the shallow trench isolation structure 5 is covered by the metal layer 7.
However, it is found in actual application that, the SOI RF device has disadvantages of great loss and poor linearity of RF signals in some RF applications requiring high linearity and low insertion loss.